The present invention relates to a design for testability technique for facilitating generation of test input patterns for fault testing of integrated circuits.
One of the conventional methods of design for testability for integrated circuits is a full-scan design method (see xe2x80x9cDigital Systems Testing and Testable Design,xe2x80x9d Computer Science Press, Chapter 9, pp. 343-395, 1990).
According to the full-scan design, all FFs (flip-flops) in the circuit are replaced with scan FFS, which are connected in the form of a shift register. Since the values of the FFs can be arbitrarily set and read through the shift register during testing, the scan FFs can be regarded as external inputs/outputs (I/Os). Therefore, for the full-scan design circuits, test input patterns achieving a high fault coverage can be easily generated with a combinational test input pattern generation algorithm.
Another example of the conventional methods of design for testability is a partial-scan design method. According to the partial-scan design, a part of the FFs in the circuit is replaced with scan FFs, which are connected in the form of a shift register. The partial scan design can reduce the area overhead, degradation in delay, and power consumption as compared to the full-scan design, but generally requires a sequential test input pattern generation algorithm to generate test input patterns. A method for selecting FFs to be replaced with scan FFs is of importance for a high fault coverage.
A method for selecting FFs to be replaced with scan FFs has been proposed which is capable of generating test input patterns of a partial-scan design circuit with a combinational test input pattern generation algorithm. It is reported that this proposed method can achieve a high fault coverage like the full-scan design (See T. Inoue et al., xe2x80x9cAn RT level Partial Scan Design Method Based on Combinational ATPG,xe2x80x9d TECHNICAL REPORT of IEICE, FTS96-67, February. 1997).
The scan design is a design for testability that replaces the existing FFs with scan FFs and connects them in the form of a shift register. In addition to the scan design, there is a test point insertion technique intended to improve the fault coverage of the circuits. More specifically, test points are inserted into signal lines having poor circuit controllability or observability (the circuit controllability is herein the degree of difficulty in setting xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d to signal lines within a circuit, and the observability is the degree of difficulty in observing the values of signal lines within a circuit) (see M. Nakao et al., xe2x80x9cAccelerated Test Points Selection Method for Scan-Based BIST,xe2x80x9d IEEE 1997 Asian Test Symposium, pp. 359-364).
With the progress in semiconductor integration technology, integrated circuits have been increasingly miniaturized, causing a significant increase in the number of FFs included in the integrated circuit. In contrast, the number of external pins of the integrated circuit has been increased only slightly due to the structure of the integrated circuit. Therefore, in the current mainstream full-scan design, a significantly increased number of scan FFs are present in a single scan path, resulting in a significant increase in the number of test input patterns by a tester.
FIG. 41 schematically shows an example of the full-scan circuit. In FIG. 41, PI1, PI2 and PI3 denote external inputs, PO1 and PO2 denote external outputs, FF1, FF2, FF3 and FF4 denote scan FFs, SI denotes scan-IN, and SO denotes scan-OUT. CK denotes a clock input, and SE denotes a scan-mode input for switching an operation of the respective scan FFs FF1 to FF4.
FIG. 42 shows a test input pattern generation model of the full-scan circuit of FIG. 41. In FIG. 42, normal data inputs of the scan FFs FF1 to FF4 are converted into pseudo external outputs PPO-FF1 to PPO-FF4, and outputs of the scan FFs FF1 to FF4 are converted into pseudo external inputs PPI-FF1 to PPI-FF4, respectively, so that the entire circuit is converted into a combinational circuit.
FIG. 43 shows test input patterns generated for the test input pattern generation model of FIG. 42. In FIG. 43, the external inputs are represented by xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d, and expected values of the external outputs are represented by xe2x80x9cHxe2x80x9d and xe2x80x9cLxe2x80x9d. The test input patterns for the test input pattern generation model as shown in FIG. 43 are herein referred to as xe2x80x9cparallel test input patternsxe2x80x9d. In FIG. 43, two parallel test input patterns V1 and V2 are generated, and therefore the number of parallel test input patterns is xe2x80x9c2xe2x80x9d.
An actually manufactured integrated circuit is a full-scan design circuit rather than the test input pattern generation model. Therefore, the parallel test input patterns as shown in FIG. 43 cannot directly be used for testing the integrated circuit with a tester. In other words, the parallel test input patterns generated for the test input pattern generation model must be converted into test input patterns of the actual full-scan design circuit.
FIG. 44 shows the parallel test input patterns of FIG. 43 converted into test input patterns for an actual full-scan design circuit. In FIG. 44, xe2x80x9cxe2x88x92xe2x80x9d indicates that no test input pattern is input, the rising edge of the clock CK indicates that a clock has been input, and xe2x80x9c*xe2x80x9d indicates that the expected values are not compared.
First, in order to set the values of the pseudo external inputs PPI-FF1 to PPI-FF4 of the first parallel test input pattern V1, of FIG. 43 to the scans FFs FF1 to FF4 of FIG. 41, respectively, the circuit of FIG. 41 is rendered in a shift mode (SE=1), and the clock CK is input four times with xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d and xe2x80x9c0xe2x80x9d being sequentially set to the scan-IN SI. Thus, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d are respectively set to the scan FFs FF1 to FF4.
Then, the circuit of FIG. 41 is rendered in a capture mode (SE=0), and the clock CK is input once, whereby the respective normal data input values are set to the scan FFs FF1 to FF4. In order to read these values from the scan-OUT SO, it is necessary to render the circuit of FIG. 41 again in the shift mode and to input values from the scan-IN SI.
Then, in order to set the values of the pseudo external inputs PPI-FF1 to PPI-FF4 of the second parallel test input pattern V2 of FIG. 43 to the scans FFs FF1 to FF4, respectively, the circuit of FIG. 41 is rendered in the shift mode (SE=1), and the clock CK is input four times with xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d being sequentially set to the scan-IN SI. Thus, xe2x80x9c0xe2x80x9d, xe2x80x9c1xe2x80x9d, xe2x80x9c0xe2x80x9d and xe2x80x9c1xe2x80x9d are respectively set to the scan FFs FF1 to FF4, as well as the normal data input values that have been set to the respective scan FFs FF1 to FF4 in the capture mode are sequentially observed from the scan-OUT SO. In other words, this operation enables observation of the external outputs of the pattern V1 as well as setting of the external outputs of the pattern V2.
Thus, by inputting all parallel test input patterns while repeatedly executing the shift mode and the capture mode, the expected values are compared.
Accordingly, the number of test input patterns by the tester of the scan design circuit can be given by the following equation:
The number of test input patterns by the tester=(the number of parallel test input patterns+1)xc3x97the maximum number of scan FFs present in a single scan path+the number of parallel test input patterns.
As can be seen from the above equation, as the number of scan FFs present in a single scan path is significantly increased, the number of test input patterns by the tester is remarkably increased. This means that the test time of an actual integrated circuit is increased, causing increased costs of the integrated circuit.
Moreover, an increased circuit scale requires a decoder circuit and a combinational circuit using a number of input variables to be tested with a large number of test input patterns.
The number of test input patterns by the tester of the partial-scan design circuit is significantly affected by the scan rate. However, the partial-scan design circuit generally requires a larger number of parallel test input patterns than that of the full-scan circuit, and therefore the test time of the partial-scan design circuit is often longer than that of the full-scan design circuit.
It is an object of the present invention to enable reduction in test time of an actual integrated circuit as a method of design for testability.
More specifically, in a first aspect of the present invention, a method of design for testability for facilitating generation of test input patterns for an integrated circuit includes the step of allocating a design for testability on a block-by-block basis of the integrated circuit so as to reduce the number of test input patterns.
According to the first aspect, a design for testability is allocated to each block of the integrated circuit so as to reduce the number of test input patterns. Such a reduced number of test input patterns enables reduction in test time of an actual integrated circuit.
In the method of design for testability according to the first aspect of the invention, the step of allocating a design for testability preferably includes a first process of obtaining the number of parallel test input patterns of each block, assuming that each block is full-scan designed, a second process of full-scan designing a block of interest and inserting a test point therein, the block of interest being a block whose number of parallel test input patterns obtained in the first process exceeds a prescribed value, and a third process of full-scan designing a block other than the block of interest.
In the method of design for testability according to the first aspect of the invention, the step of allocating a design for testability preferably includes a first process of obtaining the number of parallel test input patterns of each block, assuming that each block is full-scan designed, a second process of full-scan designing a block of interest, the block of interest being a block having a largest number of parallel test input patterns obtained in the first process, and a third process of partial-scan designing or full-scan designing a block other than the block of interest so that the number of parallel test input patterns of the block does not exceed the number of parallel test input patterns of the block of interest that is obtained in the first process.
In the method of design for testability according to the first aspect of the invention, the step of allocating a design for testability preferably includes a first process of obtaining the number of parallel test input patterns of each block, assuming that each block is full-scan designed, a second process of full-scan designing a block of interest and inserting a test point therein, the block of interest being a block whose number of parallel test input patterns obtained in the first process exceeds a prescribed value, a third process of obtaining the number of parallel test input patterns of the block of interest, and a fourth process of partial-scan designing or full-scan designing a block other than the block of interest so that the number of parallel test input patterns of the block does not exceed the number of parallel test input patterns of the block of interest that is obtained in the third process.
In the method of design for testability according to the first aspect of the invention, the step of allocating a design for testability preferably includes a process of selecting a design for testability for each block from a respective design-for-testability library according to an evaluation function of test time required for fault testing, each of the respective design-for-testability libraries of the blocks storing types of designs for testability and result information indicating results of the designs for testability.
Each of the design-for-testability libraries preferably stores as the result information the number of scan FFs (flip-flops) and the number of parallel test input patterns.
The evaluation function is preferably a product of a sum of the respective numbers of scan FFs of the blocks and a maximum value of the number of parallel test input patterns of the blocks.
In a second aspect of the present invention, a method of design for testability for facilitating generation of test input patterns for a partially scanned integrated circuit includes: a first process of finding, for each input of a plurality of blocks, which is connected in common to an output of a same block in the integrated circuit, an FF that is accessible from the input only through a combinational circuit and is not a scan FF, as well as calculating the number of such FFs for each input; a second process of selecting from the inputs connected to the output of the same block an input having a largest number of FFs obtained in the first process; and a third process of replacing every FF found in the first process with a scan FF, the third process being conducted for each of the inputs other than that selected in the second process.
In a third aspect of the present invention, a method of design for testability for facilitating generation of test input patterns for an integrated circuit includes the step of, when the integrated circuit is a combinational circuit or a full-scan design circuit, or when a block forming the integrated circuit is a combinational circuit or a full-scan design circuit, determining a test-point position so as to reduce the number of parallel test input patterns of the integrated circuit or the block, wherein a test circuit is inserted at the test-point position determined in the step.
In the method of design for testability according to the third aspect of the invention, the step of determining a test-point position preferably includes a first process of, when a plurality of selected external outputs have a common accessible external input, determining the test-point position so as to make only one of the plurality of external outputs accessible to the external input.
In the method of design for testability according to the third aspect of the invention, the step of determining a test-point position preferably includes a first process of, when the number of external inputs accessible from a selected external output is equal to or larger than a prescribed value, determining the test-point position so as to make the number of accessible external inputs smaller than the prescribed value.
The step of determining a test-point position preferably includes as a pre-process a process of calculating a fault coverage of each external output of the integrated circuit or the block, wherein the external output(s) of the first process is preferably selected based on the calculated fault coverage.
The step of determining a test-point position preferably includes as a pre-process a process of calculating the number of external inputs accessible from each external output of the integrated circuit or the block, wherein the external output(s) of the first process is preferably selected based on the calculated number of accessible external inputs.
In the method of design for testability according to the third aspect of the invention, the step of determining a test-point position preferably determines the test-point position so as to make a maximum value of a value-assignment probability of an external input smaller than a prescribed value.
In the method of design for testability according to the third aspect of the invention, the step of determining a test-point position preferably includes a first process of calculating a fault coverage of each external output of the integrated circuit or the block, and a second process of calculating as a value-assignment probability of each external input, a sum of the respective fault coverage of the external outputs accessible from the external input which are calculated in the first process, wherein the test-point position is preferably determined so that a value-assignment probability of each external input becomes lower than a prescribed value when a signal line having a test point inserted therein is regarded as an external input/output (I/O).
Preferably, a position that results in a smallest maximum value of the value-assignment probability of the external input upon tentative insertion of the test point is preferentially determined as the test-point position.
The step of determining a test-point position preferably includes a first process of calculating a fault coverage of each external output and a value-assignment probability of each signal line, a second process of selecting candidate signal lines for test-point insertion from representative signal lines, based on the calculation result of the first process, and a third process of selecting a signal line for test-point insertion from the candidate signal lines selected in the second process.
The representative signal lines are preferably fan-out stems.
Preferably, the representative signal lines are fan-out stems and have a value-assignment probability higher than a maximum value of the fault coverage of the external output as well as lower than a maximum value of the value-assignment probability of the external input.
Preferably, the second process is a process of calculating a cost of each representative signal line and preferentially selecting representative signal lines having a larger cost value as the candidate signal lines, wherein the cost is calculated by the steps of obtaining a set of external outputs accessible to the representative signal line, obtaining, for each external output of the set, a sum of differences between a prescribed threshold value of the value-assignment probability and the respective value-assignment probabilities of the external inputs that are accessible from the external output and have a value-assignment probability equal to or higher than the threshold value, and calculating as a cost value a sum of the respective sums of the external outputs of the set.
Preferably, the third process is a process of calculating a cost of each candidate signal line and preferentially selecting a candidate signal line having a larger cost value as the signal line for test-point insertion, wherein the cost is calculated by the steps of obtaining a set of external inputs accessible to the candidate signal line and having a value-assignment probability equal to or higher than a prescribed threshold value, obtaining a reduction amount for each external input of the set, the reduction amount being a sum of the respective fault coverage of the external outputs that become no longer accessible from the external input upon disconnecting the candidate signal line, and calculating as a cost value a sum of the respective reduction amounts of the external inputs of the set.
In a design-for-testability integrated circuit according to a fourth aspect of the present invention, a test circuit formed from a scan FF and a two-input selector is inserted in a signal line, the integrated circuit including a scan FF for controlling a selection signal line of the two-input selector.
In the design-for-testability integrated circuit, the scan FF is preferably formed so that its data input is fixed to a value of a selection signal for a normal operation of the two-input selector and a reset value of the scan FF at its reset input is disenabled during scan testing.
In the design-for-testability integrated circuit, the scan FF preferably has its data input fixed to a value of a selection signal for a normal operation of the two-input selector.
In the design-for-testability integrated circuit, the scan FF is preferably formed so that its data input is connected to a signal line and a reset value of the scan FF at its reset input is disenabled during scan testing.
A design method for an integrated circuit according to a fifth aspect of the present invention includes the step of selecting a design for testability for each block of the integrated circuit from a respective design-for-testability library, each of the respective design-for-testability libraries of the blocks storing types of designs for testability and result information indicating results of the designs for testability.